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general description the max5122/max5123 low-power, 12-bit, voltage-out- put, digital-to-analog converters (dacs) feature an inter- nal precision bandgap reference and output amplifier. the max5122 operates on a single +5v supply with an internal +2.5v reference, and offers a configurable output amplifier. if necessary, the user can override the on-chip, <10ppm/? voltage reference with an external reference. the max5123 has the same features as the max5122 but operates from a single +3v supply and has an internal +1.25v precision reference. the user-accessible inverting input and output of the amplifier allows specific gain con- figurations, remote sensing, and high output drive capa- bility for a wide range of force/sense applications. both devices draw only 500? of supply current, which reduces to 3? in power-down mode. in addition, their power-up reset feature allows for a user-selectable initial output state of either 0v or midscale and reduces output glitches during power-up. the serial interface is compatible with spi, qspi, and microwire, which makes the max5122/max5123 suitable for cascading multiple devices. each dac has a double-buffered input organized as an input register followed by a dac register. a 16-bit shift register loads data into the input register. the dac register may be updated independently or simultaneously with the input register. both devices are available in a 16-pin qsop package and are specified for the extended-industrial (-40? to +85?) operating temperature range. for pin-compatible 14-bit upgrades, see the max5171/max5173 data sheet; for the pin-compatible 13-bit version, see the max5132/ max5133 data sheet. applications industrial process control automatic test equipment digital offset and gain adjustment motion control microprocessor-controlled systems features ? single-supply operation +5v (max5122) +3v (max5123) ? built-in 10ppm/? max precision bandgap reference +2.5v (max5122) +1.25v (max5123) ? spi/qspi/microwire-compatible, 3-wire serial interface ? pin-programmable shutdown mode and power- up reset (0 or midscale output voltage) ? buffered output capable of driving 5k ? ? ? 100pf or 4?0ma loads ? space-saving 16-pin qsop package ? pin-compatible 13-bit upgrades available (max5132/max5133) ? pin-compatible 14-bit upgrades available (max5171/max5173) max5122/max5123 +5v/+3v, 12-bit, serial, force/sense dacs with 10ppm/? internal reference ________________________________________________________________ maxim integrated products 1 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 fb v dd refadj ref agnd pd upo dout dgnd top view max5122 max5123 qsop out rstval cs pdl clr din sclk 19-1446; rev 1; 3/04 part max5122 aeee max5122beee -40? to +85? -40? to +85? temp range pin- package 16 qsop 16 qsop pin configuration ordering information inl (lsb) ?.5 ? max5123 aeee max5123beee ? -40? to +85? -40? to +85? 16 qsop 16 qsop ? spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corp. for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com.
max5122/max5123 +5v/+3v, 12-bit, serial, force/sense dacs with 10ppm/? internal reference 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics?ax5122 (+5v) (v dd = +5v ?0%, agnd = dgnd, 33nf capacitor at refadj, internal reference, r l = 5k ? , c l = 100pf, output amplifier configured in unity-gain, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to agnd, dgnd ...............................................-0.3v to +6v agnd to dgnd.....................................................-0.3v to +0.3v digital inputs to dgnd.............................................-0.3v to +6v digital outputs (dout, upo) to dgnd .....-0.3v to (v dd + 0.3v) fb, out to agnd ......................................-0.3v to (v dd + 0.3v) ref, refadj to agnd ..............................-0.3v to (v dd + 0.3v) maximum current into any pin............................................50ma continuous power dissipation (t a = +70?) qsop (derate 8.00mw/? above +70?) .....................667mw operating temperature range ...........................-40? to +85? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? v in = 0 or v dd max5122a refadj = v dd 4.5v v dd 5.5v max5123b max5122b max5122a max5122a t a = +25? conditions pf 8 c in input capacitance ? -1 0.001 1 i in input leakage current mv 200 v hys input hysteresis v 0.8 v il input low voltage v 3 v ih input high voltage ? 3.3 7 refadj current ppm/? 10 tcv ref 3 output voltage temperature coefficient v 2.475 2.5 2.525 v ref output voltage -0.5 0.5 bits 12 n resolution ?/v 20 250 psrr power-supply rejection ratio ppm/? 10 30 tcv fs 310 full-scale temperature coefficient (note 3) lsb -1 1 dnl differential nonlinearity mv -10 10 v os offset error (note 2) mv -3 -0.2 3 ge gain error units min typ max symbol parameter i sink = 2ma i source = 2ma v 0.13 0.4 v ol output low voltage v v dd - 0.5 v oh output high voltage max5123b lsb -1 1 inl integral nonlinearity (note 1) 0 i out 100? (sourcing) ?/? 0.1 1 v out /i out reference external load regulation ma 4 reference short-circuit current static performance reference digital input digital outputs
max5122/max5123 +5v/+3v, 12-bit, serial, force/sense dacs with 10ppm/? internal reference _______________________________________________________________________________________ 3 electrical characteristics?ax5122 (+5v) (continued) (v dd = +5v ?0%, agnd = dgnd, 33nf capacitor at refadj, internal reference, r l = 5k ? , c l = 100pf, output amplifier configured in unity-gain, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) to ?.5lsb, v step = 2.5v cs = v dd , f sclk = 100khz, v sclk = 5vp-p conditions ? 320 i shdn power-supply current in shutdown ? 500 600 i dd power-supply current (note 5) v 4.5 5.5 v dd power-supply voltage (note 5) nv-sec 5 digital feedthrough ms 2 time required to exit shutdown ? 20 output settling time v 0 to v dd output voltage swing (note 4) units min typ max symbol parameter electrical characteristics?ax5123 (+3v) (v dd = +3v ?0%, agnd = dgnd, 33nf capacitor at refadj, internal reference, r l = 5k ? , c l = 100pf, output amplifier connected in unity-gain, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) max5123a refadj = v dd 2.7v v dd 3.3v max5123b max5123b max5123a max5123a t a = +25? conditions mv 200 v hys input hysteresis v 0.8 v il input low voltage v 2.2 v ih input high voltage ? 3.3 7 refadj current ma 4 reference short-circuit current ppm/? 10 tcv ref max5123b 3 0 i out 100? (sourcing) output voltage temperature coefficient v 1.237 1.25 1.263 v ref output voltage -1 1 ?/? 0.1 1 bits 12 n resolution ?/v 20 250 psrr power-supply rejection ratio ppm/? 10 30 tcv fs lsb 310 v out /i out full-scale temperature coefficient (note 3) lsb -1 1 dnl differential nonlinearity mv -10 10 v os offset error (note 2) reference external load regulation mv -5 -0.2 5 ge gain error units min typ max symbol parameter -2 2 inl integral nonlinearity (note 1) v/? 0.6 sr voltage output slew rate static performance reference digital input ? -0.1 0 0.1 current into fb dynamic performance power requirements
max5122/max5123 +5v/+3v, 12-bit, serial, force/sense dacs with 10ppm/? internal reference 4 _______________________________________________________________________________________ electrical characteristics?ax5123 (+3v) (continued) (v dd = +3v ?0%, agnd = dgnd, 33nf capacitor at refadj, internal reference, r l = 5k ? , c l = 100pf, output amplifier connected in unity-gain, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) to ?.5lsb, v step = 1.25v cs = v dd , f sclk = 100khz, v sclk = 3vp-p conditions ? 320 i shdn power-supply current in shutdown ? 500 600 i dd power-supply current (note 5) v 2.7 3.6 v dd power-supply voltage (note 5) nv-sec 5 digital feedthrough ms 2 time required to exit shutdown ? -0.1 0 0.1 current into fb ? 20 output settling time v 0 to v dd output voltage swing (note 4) units min typ max symbol parameter i sink = 2ma v 0.13 0.4 v ol output low voltage i source = 2ma v v dd - 0.5 v oh output high voltage v in = 0 or v dd ? -1 0.001 1 i in input leakage current pf 8 c in input capacitance v/? 0.6 sr voltage output slew rate timing characteristics?ax5122 (+5v) (v dd = +5v ?0%, agnd = dgnd, 33nf capacitor at refadj, internal reference, r l = 5k ? , c l = 100pf, output amplifier connected in unity-gain, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) ns 40 t css cs fall to sclk rise setup time ns 40 t cl sclk pulse width low conditions ns 100 t cp sclk clock period ns 40 t ch sclk pulse width high ns 0 t csh sclk rise to cs rise hold time ns 10 t cs0 sclk rise to cs fall delay time ns 40 t ds sdi setup time ns 0 t dh sdi hold time units min typ max symbol parameter ns 100 t csw cs pulse width high ns 40 t cs1 cs rise to sclk rise hold time c load = 200pf ns 80 t do1 sclk rise to dout valid propagation delay time c load = 200pf ns 80 t do2 sclk fall to dout valid propagation delay time digital outputs power requirements dynamic performance
max5122/max5123 +5v/+3v, 12-bit, serial, force/sense dacs with 10ppm/? internal reference _______________________________________________________________________________________ 5 note 1: accuracy is guaranteed by the following table: note 2: offset is measured at the code closest to 10mv. note 3: the temperature coefficient is determined by the ?ox?method, in which the maximum ? v out over the temperature range is divided by ? t and the typical reference voltage. note 4: accuracy is better than 1.0lsb for v out = 10mv to (v dd - 180mv). guaranteed by psr test on end points. note 5: r load = and digital inputs are at either v dd or dgnd. timing characteristics?ax5123 (+3v) (v dd = +3v ?0%, agnd = dgnd, 33nf capacitor at refadj, internal reference, r l = 5k ? , c l = 100pf, output amplifier connected in unity-gain, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) ns 60 t css cs fall to sclk rise setup time ns 150 ns c load = 200pf 75 t csw t cl sclk pulse width low conditions ns 150 t cp sclk clock period ns 75 t ch sclk pulse width high ns 0 t csh sclk rise to cs rise hold time cs pulse width high ns 75 t cs1 cs rise to sclk rise hold time c load = 200pf ns 200 t do1 sclk rise to dout valid propagation delay time ns 200 t do2 sclk fall to dout valid propagation delay time ns 10 t cs0 sclk rise to cs fall delay time ns 60 t ds sdi setup time ns 0 t dh sdi hold time units min typ max symbol parameter 16 5 33 3 4095 4095 accuracy guaranteed to code: from code: v dd (v)
max5122/max5123 +5v/+3v, 12-bit, serial, force/sense dacs with 10ppm/? internal reference 6 _______________________________________________________________________________________ t ypical operating characteristics (v dd = +5v, r l = 5k ? , c l = 100pf, output amplifier in unity-gain configuration, t a = +25?, unless otherwise noted.) 200 250 300 350 400 450 500 -60 -20 -40 0 20 4 06080100 max5122 supply current vs. temperature max5122/23 toc04 temperature (?) supply current ( a) (code = aaa hex) (code = 000 hex) 250 300 400 350 450 500 4.0 4.5 5.0 5.5 6.0 max5122 supply current vs. supply voltage max5122/23 toc05 supply voltage (v) supply current ( a) (code = aaa hex) (code = 000 hex) 0 0.25 0.50 1.00 0.75 1.25 1.75 1.50 2.00 -60 -20 -40 0 20 4 06080100 max5122 shutdown current vs. temperature max5122/23 toc06 temperature (?) shutdown current ( a) 2.490 2.495 2.500 2.505 2.510 -60 -20 -40 0 20 4 06080100 max5122 full-scale output voltage vs. temperature max5122/23 toc07 temperature (?) full-scale output (v) r l = 5k ? c l = 100pf 0.1 1 10 100 max5122 full-scale output error vs. resistive load max5122/23 toc08 r l (k ? ) full-scale output error (lsb) 0.25 -2.00 -1.25 -0.50 cs 5v/div out 1v/div 2 s/div max5122 dynamic response rise time max5122/23-09 -0.20 -0.15 -0.10 -0.05 0 0.05 0.10 0.15 0.20 0 1,000 2,000 3,000 4,000 5,000 max5122 integral nonlinearity vs. digital input code max5122/23 toc01 digital input code inl (lsb) -0.20 -0.15 -0.10 -0.05 0 0.05 0.10 0.15 0.20 0 1,000 2,000 3,000 4,000 5,000 max5122 differential nonlinearity vs. digital input code max5122/23 toc02 digital input code dnl (lsb) 2.490 2.495 2.500 2.505 2.510 -60 -20 20 60 -40 0 40 80 100 max5122 reference voltage vs. temperature max5122/23 toc03 temperature (?) reference voltage (v)
max5122/max5123 +5v/+3v, 12-bit, serial, force/sense dacs with 10ppm/? internal reference _______________________________________________________________________________________ 7 -0.20 -0.15 -0.10 0 -0.05 0.05 0.10 0.15 0.20 0.25 0 1,000 2,000 3,000 4,000 5,000 max5123 integral nonlinearity vs. digital input code max5122/23 toc13 digital input code inl (lsb) 200 250 300 350 400 -60 -20 -40 0 20 4 06080100 max5123 supply current vs. temperature max5122/23 toc16 temperature (?) supply current ( a) (code = aaa hex) (code = 000 hex) -0.25 -0.20 -0.15 -0.10 -0.05 0 0.05 0.10 0.15 0 1,000 2,000 3,000 4,000 5,000 max5123 differential nonlinearity vs. digital input code max5122/23 toc14 digital input code dnl (lsb) 1.240 1.245 1.250 1.255 1.260 -60 -20 20 60 -40 0 40 80 100 max5123 reference voltage vs. temperature max5122/23 toc15 temperature (?) reference voltage (v) 200 300 250 350 400 2.50 2.75 3.00 3.25 3.50 max5123 supply current vs. supply voltage max5122/23 toc17 supply voltage (v) supply current ( a) (code = aaa hex) (code = 000 hex) 0.1 0.2 0.3 0.4 0.5 -60 -20 -40 0 20 4 06080100 max5123 shutdown current vs. temperature max5122/23 toc18 temperature (?) shutdown current ( a) cs 5v/div out 1v/div 2 v/div max5122 dynamic response fall time max5122/23-10 sclk 2v/div out 1mv/div ac coupled 2 s/div max5122 digital feedthrough (sclk, out) max5122/23-11 cs 2v/div out 100mv/div ac coupled 5 s/div max5122 major carry transition max5122/23-12 t ypical operating characteristics (continued) (v dd = +5v, r l = 5k ? , c l = 100pf, output amplifier in unity-gain configuration, t a = +25?, unless otherwise noted.)
max5122/max5123 +5v/+3v, 12-bit, serial, force/sense dacs with 10ppm/? internal reference 8 _______________________________________________________________________________________ 1.240 1.245 1.250 1.255 1.260 -60 -20 -40 0 20 4 06080100 max5123 full-scale output voltage vs. temperature max5122/23 toc19 temperature (?) full-scale output (v) 0.01 1 0.1 10 100 max5123 full-scale output error vs. resistive load max5122/23 toc20 r l (k ? ) full-scale output error (lsb) -4 -3 -2 -1 0 cs 2v/div out 400mv/div 1 s/div max5123 dynamic-response rise time max5122/23-21 cs 2v/div out 400mv/div 1 s/div max5123 dynamic-response fall time max5122/23-22 sclk 2v/div out 500 v/div ac coupled 2 s/div max5123 digital feedthrough (sclk, out) max5122/23-23 cs 2v/div out 100mv/div ac coupled 5 v/div max5123 major carry transition max5122/23-24 t ypical operating characteristics (continued) (v dd = +5v, r l = 5k ? , c l = 100pf, output amplifier in unity-gain configuration, t a = +25?, unless otherwise noted.)
max5122/max5123 +5v/+3v, 12-bit, serial, force/sense dacs with 10ppm/? internal reference _______________________________________________________________________________________ 9 analog output voltage. high impedance if part is in shutdown. out 2 power-down lockout (digital input). 1: normal operation. 0: disallows shutdown (device cannot be powered down). pdl 4 reset value input (digital input). 1: connect to v dd to select midscale as the output reset value. 0: connect to dgnd to select 0v as the output reset value. rstval 3 active-low chip-select input (digital input) cs 6 serial clock input sclk 8 serial data input. data is clocked in on the rising edge of sclk. din 7 reset dac input (digital input). clears the dac to its predetermined (rstval) output state. clearing the dac will cause it to exit a software shutdown state. clr 5 serial data output dout 10 power-down input (digital input). pulling pd high when pdl = v dd places the ic into shutdown with a maxi- mum shutdown current of 20?. pd 12 user-programmable output (digital output) upo 11 buffered reference output/input. in internal reference mode, the reference buffer provides a +2.5v (max5122) or +1.25v (max5123) nominal output, externally adjustable at refadj. in external reference mode, disable the internal reference by pulling refadj to v dd and applying the external reference to ref. ref 14 pin positive power supply. bypass with a 0.1? capacitor in parallel with a 4.7? capacitor to agnd. v dd 16 amplifier inverting sense input (analog input) fb 1 function name analog reference adjust input. bypass with a 33nf capacitor to agnd. connect to v dd when using an external reference. refadj 15 analog ground agnd 13 digital ground dgnd 9 pin description
max5122/max5123 +5v/+3v, 12-bit, serial, force/sense dacs with 10ppm/? internal reference 10 ______________________________________________________________________________________ _______________detailed description the max5122/max5123 12-bit, force/sense dacs are easily configured with a 3-wire serial interface. they include a 16-bit data-in/data-out shift register and have a double-buffered digital input consisting of an input register and a dac register. in addition, these devices employ precision bandgap references, as well as an output amplifier with accessible feedback and output pins that can be used to set the gain externally (figure 1) or for forcing and sensing applications. these dacs are designed with an inverted r-2r ladder network (figure 2) that produces a weighted voltage proportion- al to the digital input code. internal reference both devices use an on-board precision bandgap ref- erence with a low temperature coefficient of only 10ppm/? (max) to generate an output voltage of +2.5v (max5122) or +1.25v (max5123). the ref pin can source up to 100? and may become unstable with capacitive loads exceeding 100pf. refadj can be used for minor adjustments to the reference voltage. max5122 max5123 sr control 16-bit shift register decode control input register bandgap reference reference buffer dac register dac 2x (x1) dout upo fb out 4k 1.25v 12 agnd dgnd v dd din sclk cs 2.5v (1.25v) logic output clr rstval pdl pd refadj ref ( ) are for max5123 only. figure 1. simplified functional diagram out fb note: shown for all 1s on dac. d0 d9 d10 d11 *internal reference: +2.5v (max5122), +1.25v (max5123); or external reference 2r 2r 2r 2r 2r rrr ref* agnd figure 2. simplified inverted r-2r dac structure
max5122/max5123 +5v/+3v, 12-bit, serial, force/sense dacs with 10ppm/? internal reference ______________________________________________________________________________________ 11 the circuit in figure 3 achieves a nominal reference adjustment range of ?%. connect a 33nf capacitor from refadj to agnd to establish low-noise dac operation. larger capacitor values may be used, but will result in increased start-up delay. the time constant ( ) for the start-up delay is determined by the refadj input impedance of 4k ? and c refadj : = 4k ? c refadj external reference an external reference may be applied to the ref pin. disable the internal reference by pulling refadj to v dd . this allows an external reference signal (ac- or dc-based) to be fed into the ref pin. for proper oper- ation, do not exceed the input voltage range limits of 0 to (v dd - 1.4v) for v ref . determine the output voltage using the following equa- tion (refadj = v dd ): v out = v ref [(nb / 4096) g] where nb is the numeric value of the max5122/ max5123 input code (0 to 4095), v ref is the external reference voltage, and g is the gain of the output amplifier, set by an external resistor-divider. the ref pin has a minimum input resistance of 40k ? and is code-dependent. output amplifier the max5122/max5123? dac output is internally buffered by a precision amplifier with a typical slew rate of 0.6v/?. access to the output amplifier? inverting input (fb) provides the user greater flexibility with amplifier gain setting and signal conditioning (see applications information ). the output amplifier typically settles to ?.5lsb from a full-scale transition within 20? when it is connected in unity gain and loaded with 5k ??? 100pf. loads less than 1k ? may result in degraded performance. power-down mode these devices feature software- and hardware-pro- grammable (pd pin) shutdown modes that reduce the typical supply current to 3?. to enter software shut- down mode, program the control sequence for the dac as shown in table 1. in shutdown mode, the amplifier output becomes high- impedance and the serial interface remains active. data in the input registers is saved, allowing the max5122/max5123 to recall the output state prior to entering shutdown when returning to normal operation. to exit shutdown mode, load both input and dac regis- ters simultaneously or update the dac register from the input register. when returning from shutdown to normal operation, wait 2ms for the reference to settle. when using an external reference, the dac requires only 20? for the output to stabilize. refadj +3v 15k 100k 400k 33nf max5123 refadj +5v 90k 100k 400k 33nf max5122 figure 3a. max5122 reference adjust circuit figure 3b. max5123 reference adjust circuit
max5122/max5123 +5v/+3v, 12-bit, serial, force/sense dacs with 10ppm/? internal reference 12 ______________________________________________________________________________________ power-down lockout input ( pdl ) the power-down lockout pin ( pdl ) disables shutdown when low. when in shutdown mode, a high-to-low tran- sition on pdl will wake up the dac with its output still set to the state prior to power-down. pdl can also be used to wake up the device asynchronously. power-down input (pd) pulling pd high places the max5122/max5123 in shut- down. pulling pd low will not return the max5122/ max5123 to normal operation. a high-to-low transition on pdl or appropriate commands (table 1) via the ser- ial interface are required to exit power-down mode. serial-interface configuration (spi/qspi/microwire/pic16/pic17) the max5122/max5123 3-wire serial interface is com- patible with spi, qspi, pic16/pic17 (figure 4) and microwire (figure 5) interface standards. the 2- byte-long serial input word contains three control bits, 12 data bits in msb-first format, and one sub-bit, which is always zero (table 2). the max5122/max5123? digital inputs are double buffered, which allows the user to: ? load the input register without updating the dac register, ? update the dac register with data from the input register, ? update the input and dac registers concurrently. load input register; dac register unchanged. 12-bit dac data 0 0 0 1 0 update dac register from input register; exit shutdown. xxxxxxxxxxxx 0 1 1 1 0 simultaneously load input and dac registers; exit shutdown. 12-bit dac data 0 upo goes low (default). xxxxxxxxxxxx 1 0 0 0 1 mode 1; dout clocked out on sclk? rising edge. 1xxxxxxxxxxx 1 1 1 1 0 upo goes high. xxxxxxxxxxxx 1 no operation. xxxxxxxxxxxx 0 shutdown dac (provided pdl = 1). xxxxxxxxxxxx 1 mode 0; dout clocked out on sclk? falling edge (default). 00xxxxxxxxxx 1 1 1 c1 c0 c2 function d11 ............... d0 table 1. serial-interface programming commands x = don? care * s0 is a sub-bit and always zero. din sclk cs mosi sck i/o spi/qspi port (pic16/pic17) ss v dd cpol = 0, cpha = 0 (cke = 1, ckp = 0, smp= 0 sspm3 - sspm0 = 0001) ( ) are for pic16/pic17 only. max5122 max5123 figure 4. spi/qspi interface connections (pic16/pic17) din sclk cs sk so i/o microwire port max5122 max5123 figure 5. microwire interface connections 16-bit serial word 0 s0* 0 0 0 0 0 0 0 0 s0*
max5122/max5123 +5v/+3v, 12-bit, serial, force/sense dacs with 10ppm/? internal reference ______________________________________________________________________________________ 13 the 16-bit input word may be sent in two 1-byte pack- ets (spi-, microwire-, and pic16/pic17-compatible), with cs low during this period. the control bits c2, c1, and c0 (table 1) determine: ? the clock edge on which dout transitions, ? the state of the user-programmable logic output, ? the configuration of the device after shutdown. the general timing diagram in figure 6 illustrates how data is acquired. cs must be low for the part to receive data. with cs low, data at din is clocked into the regis- ter on the rising edge of sclk. when cs transitions high, data is latched into the input and/or dac regis- ters, depending on the setting of the three control bits c2, c1, and c0. the maximum serial clock frequency guaranteed for proper operation is 10mhz for the max5122 and 6.6mhz for the max5123. figure 7 depicts a more detailed timing diagram of the serial interface. pic16 with ssp module and pic17 interface the max5122/max5123 are compatible with a pic16/pic17 microcontroller (?), using the synchro- nous serial port (ssp) module. to establish spi commu- nication, connect the controller as shown in figure 4 and configure the pic16/pic17 as system master by ini- tializing its synchronous serial port control register (ssp- con) and synchronous serial port status register (sspstat) to the bit patterns shown in tables 3 and 4. in spi mode, the pic16/pic17 ?s allow eight bits of data to be synchronously transmitted and received simultaneously. two consecutive 8-bit writings (figure 6) are necessary to feed the dac with three control bits, 12 data bits, and one sub-bit. din data transitions on the serial clock? falling edge and is clocked into the dac on sclk? rising edge. the first eight bits of din contain the three control bits (c2, c1, c0) and the first five data bits (d11?7). the second 8-bit data stream contains the remaining bits (d6?0), and the sub-bit s0. control bits msb ............................................................................... lsb d11................................d0 c2, c1, c0 cs sclk din command executed 9 8 16 1 c1 c2 s0 c0 d11 d10 d9 d8 d5 d4 d3 d2 d1 d0 d7 d6 figure 6. serial-interface timing sclk din dout t cs0 t css t cl t ch t cp t csw t cs1 t csh t ds t do1 t do2 t dh cs figure 7. detailed serial-interface timing table 2. serial data format ? 16 bits of serial data ? sub-bit s0 msb ..... data bits ..... lsb
max5122/max5123 +5v/+3v, 12-bit, serial, force/sense dacs with 10ppm/? internal reference 14 ______________________________________________________________________________________ serial data output the contents of the internal shift-register are output serially on dout which allows for daisy-chaining of multiple devices (see applications information ) as well as data readback. the max5122/max5123 may be programmed to shift data out of dout on the serial clock? rising edge (mode 1) or on the falling edge (mode 0). the latter is the default during power-up and provides a lag of 16 clock cycles, maintaining spi, qspi, microwire, and pic16/pic17 compatibility. in mode 1, the output data lags din by 15.5 clock cycles. during power-down, dout retains its last digital state prior to shutdown. user-programmable output (upo) the upo feature allows an external device to be con- trolled through the serial-interface setup (table 1) there- by reducing the number of microcontroller i/o ports required. during power-down, this output will retain the last digital state before shutdown. with clr pulled low, upo will reset to the default state after wake-up. table 3. detailed sspcon register contents receive overflow detect bit x sspov bit6 bit7 clock polarity select bit. ckp = 0 for spi master-mode selection. 0 ckp bit4 bit5 synchronous serial port enable bit. 0: disables serial port and configures these pins as i/o port pins. 1: enables serial port and configures sck, sdo and sci as serial- port pins. 1 sspen 0 sspm2 bit2 bit3 1 sspm0 bit0 bit1 control bit 0 sspm1 write collision detection bit x wcol synchronous serial-port control register (sspcon) max5122/max5123 settings synchronous serial port mode select bit. sets spi master mode and selects f clk = f osc / 16 0 sspm3 x = don? care table 4. detailed sspstat register contents x = don? care spi clock edge select bit. data will be transmitted on the rising edge of the serial clock. 1 cke bit6 buffer full status bit bit7 update address read/write bit information stop bit x p bit4 bit5 data address bit x d/a x r/w bit2 bit3 x bf bit0 bit1 control bit x ua spi data input sample phase. input data is sampled at the mid- dle of the data output time. 0 smp synchronous serial-port control register (sspstat) max5122/max5123 settings start bit x s
max5122/max5123 +5v/+3v, 12-bit, serial, force/sense dacs with 10ppm/? internal reference ______________________________________________________________________________________ 15 __________applications information definitions integral nonlinearity (inl) integral nonlinearity (figure 8a) is the deviation of the values on an actual transfer function from a straight line. this straight line can be either a best-straight-line fit (closest approximation to the actual transfer curve) or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nulli- fied. for a dac, the deviations are measured at every single step. differential nonlinearity (dnl) differential nonlinearity (figure 8b) is the difference between an actual step height and the ideal value of 1lsb. if the magnitude of the dnl is less than or equal to 1lsb, the dac guarantees no missing codes and is monotonic. offset error the offset error (figure 8c) is the difference between the ideal and the actual offset point. for a dac, the off- set point is the step value when the digital input is zero. this error affects all codes by the same amount and can usually be compensated for by trimming. gain error gain error (figure 8d) is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after nullifying the offset error. this error alters the slope of the transfer function and corre- sponds to the same percentage error in each step. 0 2 1 4 3 7 6 5 000 010 001 011 100 101 110 at step o11 (1/2 lsb ) at step 001 (1/4 lsb ) 111 digital input code analog output value (lsb) figure 8a. integral nonlinearity figure 8b. differential nonlinearity 0 2 1 4 3 6 5 000 010 001 011 100 101 differential linearity error (-1/4 lsb) differential linearity error (+1/4 lsb) 1 lsb 1 lsb digital input code analog output value (lsb) 0 2 1 3 000 010 001 011 actual diagram ideal diagram actual offset point offset error (+1 1/4 lsb) ideal offset point digital input code analog output value (lsb) figure 8c. offset error figure 8d. gain error 0 5 4 6 7 000 101 100 110 111 ideal diagram gain error (-1 1/4 lsb) ideal full-scale output actual full-scale output digital input code analog output value (lsb)
max5122/max5123 +5v/+3v, 12-bit, serial, force/sense dacs with 10ppm/? internal reference 16 ______________________________________________________________________________________ settling time the settling time is the amount of time required from the start of a transition until the dac output settles to its new output value within the converter? specified accu- racy. digital feedthrough digital feedthrough is noise generated on the dac? output when any digital input transitions. proper board layout and grounding will significantly reduce this noise, but there will always be some feedthrough caused by the dac itself. unipolar output figure 9 shows the max5122/max5123 setup for unipo- lar, rail-to-rail operation with a closed- loop gain of 2v/v. with its internal reference of +2.5v, the max5122 pro- vides a convenient unipolar output range of 0 to +4.99878v, while the max5123 offers an output range of 0 to +2.49939v with its on-board +1.25v reference. table 5 lists example codes for unipolar output voltages. bipolar output the max5122/max5123 can be configured for unity- gain bipolar operation (fb = out) using the circuit shown in figure 10. the output voltage v out is then given by the following equation: v out = v ref [{g (nb / 4096)} - 1] where nb is the numeric value of the dac? binary input code, v ref is the voltage of the internal (or exter- nal) precision reference, and g is the overall gain. the application circuit in figure 10 uses a low-cost op amp (max4162) external to the max5122/max5123. together with the max5122/max5123 this circuit offers an overall gain of +2v/v. table 6 lists example codes for bipolar output voltages. reset (rstval) and clear ( c c l l r r ) functions the max5122/max5123 dacs feature a clear pin ( clr ), which resets the output to a certain value, depending upon how rstval is set. rstval = dgnd selects an output of 0, and rstval = v dd selects a midscale out- put when clr is pulled low. the clr pin has a minimum input resistance of 40k ? in series with a diode to the supply voltage (v dd ). if the digital voltage is higher than the supply voltage for the part, a small input current may flow, but this current will be limited to (v clr - v dd - 0.5v) / 40k ? . note: clearing the dac will also cause the part to exit a software shutdown (pd = 0). daisy-chaining devices any number of max5122/max5123s may be daisy- chained by simply connecting the serial data output pin (dout) of one device to the serial data input pin (din) of the following device in the chain (figure 11). another configuration (figure 12) allows several max5122/max5123 dacs to share one common din signal line. in this configuration, the data bus is common to all devices; data is not shifted through a daisy-chain. however, more i/o lines are required in this configura- tion, because each ic needs a dedicated cs line. max5122 max5123 dac note: gain = +2v/v ref out dgnd agnd +5v/+3v v dd fb 50k 50k figure 9. unipolar output circuit using internal (+1.25v/+2.5v) or external reference. with external reference, pull refadj to v dd . max5122 max5123 max4162 dac agnd dgnd ref v out fb +5v/+3v 50k 50k v+ v- v dd out figure 10. unity-gain bipolar output circuit using internal (+1.25v/+2.5v) or external reference. with external reference, pull refadj to v dd .
max5122/max5123 +5v/+3v, 12-bit, serial, force/sense dacs with 10ppm/? internal reference ______________________________________________________________________________________ 17 v ref (2049 / 4096) 2 1000 0000 0001 0 0 v ref (2047 / 4096) 2 0111 1111 1111 0 0 v ref (2048 / 4096) 2 1000 0000 0000 0 0000 0000 0000 0 0 v ref (4095 / 4096) 2 1111 1111 1111 v ref (1 / 4096) 2 0000 0000 0001 dac contents sub-bit s0 external reference max5122/max5123 v ref [ {2 (2049 / 4096)} - 1] 1000 0000 0001 0 0 +610.35? +1.24939v dac contents v ref [ {2 (2047 / 4096)} - 1] 0111 1111 1111 0 0 -610.35? 0v v ref [ {2 (2048 / 4096)} - 1] 1000 0000 0000 -v ref 0000 0000 0000 0 0 -1.25v -1.24939v v ref [ {2 (4095 / 4096)} - 1] 1111 1111 1111 v ref [ {2 (1 / 4096)} - 1] 0000 0000 0001 table 5. unipolar code table (figure 9) table 6. bipolar code table (figure 10) +2.50122v +4.99878v +1.25061v +2.49939v +2.49878v +2.5v +1.24939v +1.25v max5122 max5123 0v +1.2207mv 0v +610.35? internal reference msb lsb analog output analog output +1.2207mv +2.49878v -1.2207mv 0v -2.5v -2.49878v to other serial devices max5122 max5123 din sclk cs max5122 max5123 max5122 max5123 din dout dout dout sclk cs iii iii din sclk cs figure 11. daisy-chaining multiple devices with the digital i/os din/dout internal reference sub-bit s0 max5123 external reference max5122/max5123 max5122 msb lsb
max5122/max5123 +5v/+3v, 12-bit, serial, force/sense dacs with 10ppm/? internal reference 18 ______________________________________________________________________________________ using an external reference with ac components the max5122/max5123 have multiplying capabilities within the reference input voltage range specifications. figure 13 shows a technique for applying a sinusoidal input to ref, where the ac signal is offset before being applied to the reference input. power-supply and bypassing considerations on power-up, the input and dac registers are cleared to either zero (rstval = dgnd) or midscale (rstval = v dd ). bypass the power supply (v dd ) with a 4.7? capacitor in parallel with a 0.1? capacitor to agnd. minimize lead lengths to reduce lead inductance. layout considerations digital and ac signals coupling to agnd can create noise at the output. connect agnd to the highest quali- ty ground available. use proper grounding techniques, such as a multilayer board with a low-inductance ground plane. wire-wrapped boards and sockets are not recommended. if noise becomes an issue, shield- ing may be required. to other serial devices max5122 max5123 din sclk cs max5122 max5123 din sclk cs max5122 max5123 din iii iii sclk cs din sclk cs1 cs2 cs3 figure 12. multiple devices share one common digital input (din) dac out max5122 max5123 10k 26k ref fb v dd dgnd agnd +5v/ +3v ac reference input 500mvp-p max495 +5v/+3v ___________________chip information transistor count: 3308 substrate connected to agnd figure 13. external reference with ac components
max5122/max5123 +5v/+3v, 12-bit, serial, force/sense dacs with 10ppm/? internal reference qsop.eps package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 19 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products.

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